View MAX5180_140691.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1577; Rev 0; 10/99
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs
General Description
The MAX5180 contains two 10-bit, simultaneousupdate, current output digital-to-analog converters (DACs) designed for superior performance in communications systems requiring analog signal reconstruction with low distortion and low-power operation. The MAX5183 provides equal specifications, with on-chip precision resistors for voltage output operation. Both devices are designed for 10pVs glitch operation to minimize unwanted spurious signal components at the output. An on-board +1.2V bandgap circuit provides a well-regulated, low-noise reference that can be disabled for external reference operation. The MAX5180/MAX5183 are designed to provide a high level of signal integrity for the least amount of power dissipation. Both DACs operate from a single supply of +2.7V to +3.3V. Additionally, these DACs have three modes of operation: normal, low-power standby, and complete shutdown, which provides the lowest possible power dissipation with 1A (max) shutdown current. A fast wake-up time (0.5s) from standby mode to full DAC operation conserves power by activating the DACs only when required. The MAX5180/MAX5183 are packaged in a 28-pin QSOP and are specified for the extended (-40C to +85C) temperature range. For lower-resolution, dual 8-bit versions, refer to the MAX5186/MAX5189 data sheet.
Features
o +2.7V to +3.3V Single-Supply Operation o Wide Spurious-Free Dynamic Range: 70dB at fOUT = 2.2MHz o Fully Differential Outputs for Each DAC o 0.5% FSR Gain Mismatch o 0.2 Phase Mismatch o Low-Current Standby or Full Shutdown Modes o Internal +1.2V Low-Noise Bandgap Reference o Small 28-Pin QSOP Package
MAX5180/MAX5183
Ordering Information
PART MAX5180BEEI MAX5183BEEI TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 QSOP 28 QSOP
Pin Configuration Applications
Signal Reconstruction of I and Q Transmit Signals Digital Signal Processing Arbitrary Waveform Generation (AWG) Imaging
TOP VIEW
CREF1 1 OUT1P 2 OUT1N 3 AGND 4 AVDD 5 DACEN 6 PD 7 CS 8 CLK 9 N.C. 10 REN 11 D0 12 D1 13 D2 14 28 CREF2 27 OUT2P 26 OUT2N 25 REFO 24 REFR
MAX5180 MAX5183
23 DGND 22 DVDD 21 D9 20 D8 19 D7 18 D6 17 D5 16 D4 15 D3
QSOP ________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to AGND, DGND .................................-0.3V to +6V Digital Inputs to DGND.............................................-0.3V to +6V OUT1P, OUT1N, OUT2P, OUT2N, CREF1, CREF2 to AGND ...................................................-0.3V to +6V VREF to AGND ..........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AVDD to DVDD .................................................................... 3.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 9.00mW/C above +70C)....... 725mW Operating Temperature Range MAX518_BEEI.................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) ............................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +3V 10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Full-Scale Error DYNAMIC PERFORMANCE Output Settling Time Glitch Impulse Spurious-Free Dynamic Range to Nyquist Total Harmonic Distortion to Nyquist Signal-to-Noise Ratio to Nyquist DAC-to-DAC Output Isolation Clock and Data Feedthrough Output Noise Gain Mismatch Between DAC Outputs Phase Mismatch Between DAC Outputs ANALOG OUTPUT Full-Scale Output Voltage Voltage Compliance of Output Output Leakage Current Full-Scale Output Current DAC External Output Resistor Load IFS RL DACEN = 0, MAX5180 only MAX5180 only MAX5180 only VFS -0.3 -1 0.5 1 400 400 0.8 1 1.5 mV V A mA fOUT = 2.2MHz fOUT = 2.2MHz SFDR THD SNR fCLK = 40MHz fCLK = 40MHz fCLK = 40MHz fOUT = 2.2MHz All 0s to all 1s fOUT = 550kHz fOUT = 2.2MHz fOUT = 550kHz fOUT = 2.2MHz fOUT = 550kHz fOUT = 2.2MHz 56 57 To 0.5LSB error band 25 10 72 70 -70 -68 61 59 -60 50 10 0.5 0.15 1 -63 ns pVs dBc dB dB dB nVs pA/Hz %FSR degrees N INL DNL Guaranteed monotonic MAX5180 MAX5183 (Note 1) 10 -2 -1 -2 -8 -40 15 0.5 0.5 +2 +1 +2 +8 +40 Bits LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
_______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +3V 10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER REFERENCE Output Voltage Range Output Voltage Temperature Drift Reference Output Drive Capability Reference Supply Rejection Current Gain (IFS / IREF) POWER REQUIREMENTS Analog Power-Supply Voltage Analog Supply Current Digital Power-Supply Voltage Digital Supply Current Standby Current Shutdown Current LOGIC INPUTS AND OUTPUTS Digital Input Voltage High Digital Input Voltage Low Digital Input Current Digital Input Capacitance TIMING CHARACTERISTICS DAC1 DATA to CLK Rise Setup Time DAC2 DATA to CLK Fall Setup Time DAC1 CLK Rise to DATA Hold Time DAC2 CLK Fall to DATA Hold Time CS Fall to CLK Rise Time CS Fall to CLK Fall Time DACEN Rise Time to VOUT_ PD Fall Time to VOUT_ Clock Period Clock High Time Clock Low Time tCP tCH tCL 25 10 10 tDS1 tDS2 tDH1 tDH2 10 10 0 0 5 5 0.5 50 ns ns ns ns ns ns s s ns ns ns 3 VIH VIL IIN CIN VIN = 0 or DVDD 10 2 0.8 1 V V A pF AVDD IAVDD DVDD IDVDD ISTANDBY ISHDN PD = 0, DACEN = 1, digital inputs at 0 or DVDD PD = 0, DACEN = 0, digital inputs at 0 or DVDD PD = 1, DACEN = X, digital inputs at 0 or DVDD (X = don't care) PD = 0, DACEN = 1, digital inputs at 0 or DVDD 2.7 4.2 1.0 0.5 2.7 2.7 3.3 5.0 3.3 5.0 1.5 1.0 V mA V mA mA A VREF TCVREF IREFOUT 1.12 1.2 50 10 0.5 8 1.28 V ppm/C A mV/V mA/mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5180/MAX5183
_______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
Typical Operating Characteristics
(AVDD = DVDD = +3V, AGND = DGND = 0, 400 differential output, IFS = 1mA, CL = 5pF, TA = +25C, unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5180/83-03
INTEGRAL NONLINEARITY vs. INPUT CODE
MAX5180/83-01
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
MAX5180/83-02
0.6 0.5 0.4
0.4 0.3 0.2
2.55
2.53 SUPPLY CURRENT (mA)
MAX5183 MAX5180
0.3 INL (LSB) DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024 INPUT CODE 0.2 0.1 0 -0.1 -0.2 0 128 256 384 512 640 768 896 1024 INPUT CODE
2.51
2.49
2.47
2.45 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5180/83-04
DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5180/83-05
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX5180/83-06
4.0 ANALOG SUPPLY CURRENT (mA)
10 DIGITAL SUPPLY CURRENT (mA)
5 DIGITAL SUPPLY CURRENT (mA) MAX5183 4
3.5
8 MAX5180 MAX5183 4
3.0 MAX5183 2.5 MAX5180
6
3 MAX5180
2
2.0
2
1
1.5 -40 -15 10 35 60 85 TEMPERATURE (C)
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX5180/83-07
STANDBY CURRENT vs. TEMPERATURE
MAX5180/83-08
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX5180/83-09
610
600 590 STANDBY CURRENT (A) MAX5183 580 570 MAX5180 560 550 540
0.80 0.75 SHUITDOWN CURRENT (A) 0.70 MAX5183 0.65 0.60 0.55 0.50 0.45 MAX5180
STANDBY CURRENT (A)
600 MAX5180 590
580 MAX5183 570
560 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs
Typical Operating Characteristics (continued)
(AVDD = DVDD = +3V, AGND = DGND = 0, 400 differential output, IFS = 1mA, CL = 5pF, TA = +25C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX5180/83-10
MAX5180/MAX5183
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX5180/83-11
OUTPUT CURRENT vs. REFERENCE CURRENT
MAX5180/83-12
1.28
1.28
4
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1.27
1.27
1.26 MAX5180 MAX5183 1.24
1.26 MAX5183 1.25 MAX5180 1.24
OUTPUT CURRENT (mA)
3
2
1.25
1
1.23 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
1.23 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 100 200 300 400 500 REFERENCE CURRENT (A)
DYNAMIC RESPONSE RISE TIME
MAX5180/83-13
DYNAMIC RESPONSE FALL TIME
MAX5180/83-14
SETTLING TIME
MAX5180/83-15
OUT_P 150mV/ div
OUT_P 150mV/ div
OUT_N 100mV/ div
OUT_N 150mV/ div
OUT_N 150mV/ div
OUT_P 100mV/ div
50ns/div
50ns/div
12.5ns/div
FFT PLOT, DAC1
MAX5180/83-16
FFT PLOT, DAC2
MAX5180/83-17
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY
MAX5180/83-18
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 2 4 6 8
fOUT = 2.2MHz fCLK = 40MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
fOUT = 2.2MHz fCLK = 40MHz
100 90 80 SFDR (dBc) DAC2 70 60 50 40 DAC1
(dBc)
(dBc)
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
10 15 20 25 30 35 40 45 50 55 60 CLOCK FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
_______________________________________________________________________________________
5
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
Typical Operating Characteristics (continued)
(AVDD = DVDD = +3V, AGND = DGND = 0, 400 differential output, IFS = 1mA, CL = 5pF, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY, DAC1
MAX5180/83-19
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY, DAC2
MAX5180/83-20
SIGNAL-TO-NOISE PLUS DISTORTION vs. OUTPUT FREQUENCY
MAX5180/83-21
78 76 74 SFDR (dBc) 72 70 68 66 fCLK = 60MHz fCLK = 40MHz
78 fCLK = 50MHz fCLK = 20MHz fCLK = 40MHz 76 74 SFDR (dBc)
62.5
fCLK = 20MHz
62.0
SINAD (dB)
61.5
DAC2 DAC1
72 70 68 66 fCLK = 10MHz fCLK = 60MHz
61.0
fCLK = 50MHz fCLK = 10MHz fCLK = 30MHz 500 700 900 1100 1300 1500 1700 1900 2100 2300 OUTPUT FREQUENCY (kHz)
60.5 fCLK = 30MHz 60.0 500 700 900 1100 1300 1500 1700 1900 2100 2300 OUTPUT FREQUENCY (kHz) 0 500 1000 1500 2000 2500 OUPUT FREQUENCY (kHz)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
MAX5180/83-22
MULITONE SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
MAX5180/83-23
SPURIOUS-FREE DYNAMIC RANGE vs. FULL-SCALE OUTPUT CURRENT
MAX5180/83-24
20 0 -20 -40 SFDR (dBc)
20 0 -20 SFDR (dBc)
74 72 70 SFDR (dBc) 68 66 64 62 60
-40 -60 -80 -100 -120 -140
-60 -80 -100 -120 -140 -160 0 5 10 15 20 25 30 OUTPUT FREQUENCY (MHz)
0
2
4
6
8
10 12 14 16 18 20
0.5
0.75
1
1.25
1.5
OUTPUT FREQUENCY (MHz)
FULL-SCALE OUTPUT CURRENT (mA)
6
_______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs
______________________________________________________________Pin Description
PIN 1 2 3 4 5 NAME CREF1 OUT1P OUT1N AGND AVDD Reference Bias Bypass, DAC1 Positive Analog Output, DAC1. Current output for MAX5180; voltage output for MAX5183. Negative Analog Output, DAC1. Current output for MAX5180; voltage output for MAX5183. Analog Ground Analog Positive Supply, +2.7V to +3.3V DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND 1: Power-up DAC with PD = DGND X: Enter shutdown mode with PD = DVDD (X = don't care) Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD) 1: Enter shutdown mode. Active-Low Chip Select Clock Input No Connect. Do not connect to this pin. Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference. Data Bit D0 (LSB) Data Bits D1-D8 Data Bit D9 (MSB) Digital Supply, +2.7V to +3.3V Digital Ground Reference Input Reference Output Negative Analog Output, DAC2. Current output for MAX5180; voltage output for MAX5183. Positive Analog Output, DAC2. Current output for MAX5180; voltage output for MAX5183. Reference Bias Bypass, DAC2 FUNCTION
MAX5180/MAX5183
6
DACEN
7 8 9 10 11 12 13-20 21 22 23 24 25 26 27 28
PD CS CLK N.C. REN D0 D1-D8 D9 DVDD DGND REFR REFO OUT2N OUT2P CREF2
_______________________________________________________________________________________
7
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
REN 1.2V REF AVDD AGND CS DACEN PD
REFO REFR CURRENTSOURCE ARRAY
CREF1 CREF2
OUT1P *9.6k DAC 1 SWITCHES DAC 2 SWITCHES 400* 400 * 400* OUTPUT LATCHES MSB DECODE CLK INPUT LATCHES OUTPUT LATCHES MSB DECODE INPUT LATCHES 400* OUT1N OUT2P OUT2N
MAX5180 MAX5183
DVDD DGND
*INTERNAL 400 AND 9.6k RESISTORS FOR MAX5183 ONLY.
D9-D0
Figure 1. Functional Diagram
Detailed Description
The MAX5180/MAX5183 are dual 10-bit digital-to-analog converters (DACs) capable of operating with clock speeds up to 40MHz. Each of these dual converters consists of separate input and DAC registers, followed by a current source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated +1.2V voltage reference and control amplifier determine the data converters' full-scale output currents/ voltages. Careful reference design ensures close gain matching and excellent drift characteristics. The MAX5183's voltage output operation features matched 400 on-chip resistors that convert the current array current into a voltage.
10A output drive capability, REFO must be buffered with an external amplifier if heavier loading is required. The MAX5180/MAX5183 also employ a control amplifier designed to simultaneously regulate the full-scale output current (IFS) for both outputs of the devices. The output current is calculated as follows: IFS = 8 * IREF where I REF is the reference output current (I REF = VREFO/RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier's output current on the MAX5180 (Figure 2). This current is mirrored into the current-source array where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. The MAX5183 converts each output current (DAC1 and DAC2) into an output voltage (VOUT1, VOUT2) with two internal, ground-referenced 400 load resistors. Using the internal +1.2V reference voltage, the MAX5183's integrated reference output current resistor (RSET = 9.6k) sets IREF to 125A and IFS to 1mA.
Internal Reference and Control Amplifier
The MAX5180/MAX5183 provide an integrated 50ppm/C, +1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to AGND, the internal reference is selected and REFO provides a +1.2V output. Due to its limited
8
_______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS REN MAX4040 +1.2V BANDGAP REFERENCE REFO CCOMP* REFR AGND IREF = VREF RSET AGND *COMPENSATION CAPACITOR (CCOMP 100nF). **9.6k REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5183 ONLY. USE EXTERNAL RSET FOR MAX5180. RSET CURRENTSOURCE ARRAY IFS AGND
IREF
RSET ** 9.6k
MAX5180 MAX5183
Figure 2. Setting IFS with the Internal +1.2V Reference and the Control Amplifier
AVDD 10F REN +1.2V BANDGAP REFERENCE REFO CURRENTSOURCE ARRAY IREF RSET RSET 9.6k* IFS AGND 0.1F
AVDD
EXTERNAL +1.2V REFERENCE
REFR
MAX6520
AGND
AGND
MAX5180 MAX5183
*9.6k REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5183 ONLY. USE EXTERNAL RSET FOR MAX5180.
Figure 3. MAX5180/MAX5183 with External Reference
_______________________________________________________________________________________
9
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
External Reference
To disable the MAX5180/MAX5183's internal reference, connect REN to AVDD. A temperature-stable, external reference may now be applied to drive the REFO pin to set the full-scale output (Figure 3). Choose a reference capable of supplying at least 150A to drive the bias circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such as the +1.2V, 25ppm/C MAX6520 bandgap reference.
Shutdown Mode
For lowest power consumption, the MAX5180/MAX5183 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the DAC supply current is reduced to 1A. To enter this mode, connect PD to DVDD. To return to active mode, connect PD to DGND and DACEN to DVDD. Table 1 lists the power-down mode selection. About 50s are required for the parts to leave shutdown mode and settle to their outputs' values prior to shutdown.
Standby Mode
To enter the lower power standby mode, connect digital inputs PD and DACEN to DGND. In standby, both the reference and the control amplifier are active with the current array inactive. To exit this condition, DACEN must be pulled high with PD held at DGND. Both the MAX5180 and MAX5183 typically require 50s to wake up and allow both the outputs and the reference to settle.
Timing Information
Both DAC cells in the MAX5180/MAX5183 write to their outputs simultaneously (Figure 4). The input latch of the first DAC (DAC1) is loaded after the clock signal transitions high. When the clock signal transitions low, the input latch of the second DAC (DAC2) is loaded. Simultaneously at the rising edge of the next clock, the contents of both input latches are shifted to the DAC registers and their outputs are updated.
tCP
tCL
tCH
CLK N-1 D0-D9 tDS1 DAC1 tDS2 DAC2 N-1 DAC1 tDH1 N DAC2 tDH2 N DAC1 N+1 DAC2 N+1
OUT1
N-1
N
N+1
OUT2
N-1
N
N+1
Figure 4. Timing Diagram
Table 1. Power-Down Mode Selection
PD (POWER-DOWN SELECT) 0 0 1 X = Don't care 10 ______________________________________________________________________________________ DACEN (DAC ENABLE) 0 1 X POWER-DOWN MODE Standby Wake-Up Shutdown OUTPUT STATE MAX5180 MAX5183 MAX5180 MAX5183 High-Z AGND High-Z AGND
Last state prior to standby mode
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs
Outputs
The MAX5180 outputs are designed to supply full-scale output currents of 1mA into 400 loads in parallel with a capacitive load of 5pF. The MAX5183 features integrated 400 resistors that restore the array currents to proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a single-ended voltage. transfer curve) or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. For a DAC, the deviations are measured every single step. Differential Nonlinearity Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Offset Error Offset error (Figure 5c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated by trimming.
MAX5180/MAX5183
Applications Information
Static and Dynamic Performance Definitions
Integral Nonlinearity Integral nonlinearity (INL) (Figure 5a) is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual
7 6 ANALOG OUTPUT VALUE 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4 LSB ) AT STEP 011 (1/2 LSB ) ANALOG OUTPUT VALUE
6 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-1/4 LSB)
Figure 5a. Integral Nonlinearity
Figure 5b. Differential Nonlinearity
3 ANALOG OUTPUT VALUE
ACTUAL DIAGRAM ANALOG OUTPUT VALUE
7
IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4 LSB)
6 IDEAL DIAGRAM 5 ACTUAL FULL-SCALE OUTPUT
2 IDEAL DIAGRAM 1 ACTUAL OFFSET POINT IDEAL OFFSET POINT 000 001
OFFSET ERROR (+1 1/4 LSB)
4 0
0
010
011
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 5c. Offset Error
Figure 5d. Gain Error 11
______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
Gain Error Gain error (Figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time Settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is the noise generated on a DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first five harmonics to the fundamental itself. This is expressed as:
2 2 2 2 V2 + V3 + V4 + V5 THD = 20 log V1
amplitude modulation) architectures where I and Q data are interleaved on a common data bus. A QAM signal is a carrier frequency that is both amplitude and phase modulated, and is created by summing two independently modulated carriers of identical frequency but different phase (90 phase difference). In a typical QAM application (Figure 7), the modulation occurs in the digital domain and the MAX5180/ MAX5183's dual DACs may be used to reconstruct the analog I and Q components. The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed I and Q components with in-phase and quadrature phase carrier frequencies, then sums both outputs to provide the QAM signal.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the MAX5180/MAX5183's performance. Unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifications like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5180/MAX5183. Therefore, grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. First, a multilayer pc board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled impedance lines directly above the ground plane. Since the MAX5180/ MAX5183 have separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Both devices have two power-supply inputs: analog VDD (AVDD) and digital VDD (DVDD). Each AVDD input should be decoupled with parallel 10F and 0.1F ceramic-chip capacitors. These capacitors should be as close to the pin as possible, and their opposite ends should be as close to the ground plane as possible. The DVDD pins should also have separate 10F and 0.1F capacitors adjacent to their respective pins. Try to minimize analog load capacitance for proper operation. For best performance, it is recommended to bypass CREF1 and CREF2 with low-ESR 0.1F capacitors to AVDD.
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the MAX5180. The differential voltage across OUT1P (or OUT2P) and OUT1N (or OUT2N) is converted into a single-ended voltage by designing an appropriate operational amplifier configuration (Figure 6).
I/Q Reconstruction in a QAM Application
The MAX5180/MAX5183's low-distortion supports analog reconstruction of in-phase (I) and quadrature (Q) carrier components typically used in QAM (quadrature
12
______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
+3V +3V 10F 0.1F AVDD DVDD CREF1 CREF2 CLK OUT1P OUTPUT1 400* MAX4108 -5V OUT1N 402 400* 402 REFO 0.1F OUT2P OUTPUT2 400* REFR RSET** OUT2N 402 400* DGND REN AGND 402 MAX4108 -5V 402 +5V 402 402 402 +5V 10F 0.1F 0.1F 0.1F AVDD AVDD
D0-D9
MAX5180 MAX5183
*400 RESISTORS INTERNAL TO MAX5183 ONLY. **MAX5180 ONLY
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can also improve performance.
Chip Information
TRANSISTOR COUNT: 9464 SUBSTRATE CONNECTED TO AGND
______________________________________________________________________________________
13
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
+3V +3V +3V
DAC1
I COMPONENT
BP FILTER
DIGITAL SIGNAL PROCESSOR
MAX5180 MAX5183
CARRIER FREQUENCY
0 90
IF
Q COMPONENT DAC2
BP FILTER
MAX2452
QUADRATURE MODULATOR
Figure 7. Using the MAX5180/MAX5183 for I/Q Signal Reconstruction
14
______________________________________________________________________________________
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs
Package Information
QSOP.EPS
MAX5180/MAX5183
______________________________________________________________________________________
15
Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs MAX5180/MAX5183
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX5180

	To Download MAX5180 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .